1. Field of the Invention
This invention relates to the dynamic random access memories (DRAM) and more particularly to the structures and methods of fabrication of DRAM's with charge amplification.
2. Description of Related Art
The fabrication and structure of DRAM cells and DRAM array are well known in the art. Typical cell structures for high density DRAM in prior art is composed of one transistor M1 10 for switching charges and one storage capacitor C 15 for storing charges as illustrated in FIG. 1a. The transistor M1 10 will be an n-MOS transistor fabricated in a triple well as shown in FIG. 1b. A deep N-well 35 will be formed in a p-type substrate 30. The area for the deep n-well 35 will be formed as openings during the formation of the insulation are by the local oxidation of the silicon substrate (LOCOS) 45. Within the deep n-well 35 a shallower p-well well 40 will be formed. The gate 60 of the n-MOS transistor M1 10 will be formed as a conductive material such as polysilicon placed over an insulating gate oxide 55 to define the channel area that will between the drain 50 and source 80 of the n-MOS transistor M1 10.
The capacitor C 15 is formed by placing a conductive metal connected to the substrate biasing voltage source V.sub.ss 75 on a dielectric 70 placed over the N.sup.+ drain 80 of the transistor M1 10. The capacitor C 15 as shown is diagrammatic. The particular structure of the capacitor C 15 is well known and shown in "The Evolution Of DRAM Cell Technology" by B. El-Kareh et al., Solid State Technology, May 1997, pp. 89-101. In order to maintain the minimum storage capacitance of 30-40 fF of a cell, the structure of the DRAM cell results in complex semiconductor processing to develop these structures.
A corresponding DRAM cell using p-MOS transistor can certainly be used with polarity and operation bias reversed accordingly.
The deep n-well 35 is typically biased to the power supply voltage source V.sub.cc (i.e. the highest potential on chip) and the p-well is biased to substrate biasing voltage source V.sub.ss 75 (i.e. the lowest voltage on chip). The substrate biasing voltage source V.sub.ss 75 may be biased below ground (i.e. negative potential) so that the leakage current through the pass transistor M.sub.1 10 is reduced. The presence of charge in the storage capacitor C 15 indicates a logical "1" and its absence of charge indicates a logical "0". The storage capacitor C 15 is connected to n+drain 80 of the transistor M.sub.1 10, and the other n+ source 50 of the transistor M.sub.1 10 is connected to bit-line V.sub.bit 25 that controls the reading and writing of the DRAM cell. The gate of the MOS transistor M1 10 is connected to the word line V.sub.word to control the selection of the DRAM cell.
The DRAM cells Cell 11 200, Cell 12 205, Cell 21 210, Cell 22 215 are arranged in arrays of rows (word-lines WL0, WL1, WL2, and WL3,) and columns (bit-lines or BL0 and BL1) as shown in FIG. 2. One popular DRAM array is the folded bit-line architecture. Each pair of bit-lines BL0 and BL1 is connected to one sense amplifier 220 where one Bit-lines BL0 or BL1 serves as reference bias and the other BIT-LINES BL0 or BL1 serves as bit-line sensing during read operation. During write operation, the bit-line BL0 and BL1 is charged to either V.sub.cc to write a logical "1" or V.sub.ss to write a logical "0". The selected word-line WL0, WL1, WL2, or WL3 is charged to V.sub.cc so that all transistors connected to the same row turn on and the capacitor of each cell are charged to V.sub.cc or V.sub.ss representing information of "1" and "0" respectively. Before read operation starts, the bit-lines BL0 and BL1 are precharged to a voltage V.sub.cc /2. To start reading a cell, the selected word-line WL0, WL1, WL2, or WL3 is raised to V.sub.cc, turning on all transistors connected to the word-line WL0, WL1, WL2, or WL3. Each sense amplifier 220 detects the polarity of charge stored on capacitor C with respect to the reference Bit-lines BL0 and BL1 voltage (i.e. V.sub.cc /2).
The signal appearing at the input of sense amplifier 220 is very small (.about.100-200 mv), since the cell capacitance is small (&lt;10%) compared to the bit-line capacitance. Throughout generations of DRAM, the minimum storage capacitance C needs to be 30-40 fF as described above in order to maintain read performance.
The requirement of large storage capacitance of conventional one-transistor cell results in high and multi-layered stack or deep trench capacitors, which is one of the major scaling limits in DRAM technology. Therefore, there is a need for innovations for reducing the requirement of storage capacitance in DRAM cell. One DRAM cell of the prior art adds a bipolar transistor to the DRAM cell for charge amplification as shown in FIG. 3a. DRAM cells with charge amplification are disclosed in U.S. Pat. No. 4,677,589 (Haskell et al.) and U.S. Pat. No. 5,363,325 (Sunouchi et al.) and shown in FIG. 3a and 3b. The structure of the cell is similar to that of FIGS. 1a and 1b. The n-MOS transistor M1 300 acts to switch the charges to and from the capacitor C 315. However, transistor Q1 310 acts to amplify the signal developed by the charges present on the capacitor to allow smaller charges to be present and still detect the logical "1" or the logical "0". The write of a logical "1" occurs when the bit-lines V.sub.bit 320 is brought to the voltage level V.sub.cc. This will allow the p/n junction formed by the emitter-base 350 of the bipolar transistor Q1 310 to conduct thus charging the capacitor C 305 to nearly the value of the power supply voltage source V.sub.cc.
When the cell is to be written to logical "0", the bipolar transistor Q1 310 will be nonconducting and any charge present on the capacitor C 305 will have to leak through parasitic paths from the capacitor C 315. This will cause the writing of a logical "0" to be very slow.
The structure of the bipolar transistor Q1 310 is formed by diffusing a p.sup.+ emitter 352 in the area that forms the N source of the n-MOS transistor M1 300. The bipolar transistor Q1 310 is thus formed as a merged transistor with the n-MOS transistor M1 300 by the p.sup.+ emitter 352, the N-base 350 (also the source of the n-MOS transistor M1 300), and the p-well 340 that acts as the collector.
"A Complementary Gain Cell Technology For Sub-1 v Supply Dram's", Shukuri et al., Digest of IEDM, p. 1006, 1992 and "Super-Low-Voltage Operation Of Semi-Static Complementary Gain DRAM Memory Cell", Shukuri et al., Digest of VLSI Technology Symposium, p. 23, 1993 describes a DRAM cell incorporating charge amplification. A complementary cell that has an n-MOS transistor and a p-MOS transistor with a floating gate structure acts as the storage node. The floating gate stores the charge representing the logical "1" or logical "0" and causes a shift in the threshold voltage of the pMOS transistor to allow reading of the logical "1" or logical "0" from the storage cell. "A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Dram's", M. Terauchi, et. al., Digest of VLSI Technology Symposium, p. 21, 1993 discloses a surrounding gate transistor gain cell. The surrounding gate transistor cell has an n-MOS transistor, a junction field effect transistor (FET), and a charge storage capacitor. The charge storage capacitor is formed as the gate of the junction FET.
"A Novel Merged Gain Cell For Logic Compatible High Density Dram's", M. Mukai, et. al., Digest of VLSI Technology Symposium, p. 155, 1997 discloses a merged DRAM cell that has a p-MOS transistor, an n-MOS transistor, a n-type junction FET, a second bit-line for write operation. The p-MOS transistor controls the charge transfer, the n-MOS transistor is used for charge storage and a read transistor, and the n-type junction FET is used to control the read out current. The charge storage occurs in the channel region of the n-MOS transistor.
The write and read operations of the DRAM cell of Shukuri et al., M. Terauchi, et. al., and M. Mukai, et. al., are handled by separate transistors and bit-lines to avoid the slow discharging as the bipolar/MOS transistor gain cell of FIGS. 3a and 3b as above described.
U.S. Pat. No. 5,066,607 (Banerjee) teaches a two transistor gain type DRAM cell. The two transistor DRAM cell has a high quality pass transistor and a large capacitance storage element. The gate of a gain transistor is coupled between the storage element and the pass transistor to amplify the charge at the storage element during a read operation.
U.S. Pat. No. 4,791,611 (Eldin et al.) discloses a memory cell that includes a bipolar transistor, a junction FET, and a capacitor. The capacitor comprises a MOSFET which is operated in the accumulation mode. The bipolar transistor controls the writing of the capacitor, while the junction FET controls the reading of the data from the capacitor.